There is a gotcha in the Verilog where you find very trouble in debugging the tasks in the modules. You got to be careful as all the entities in the module are static rather than dynamic. 1 2 module test ; 3 task delayPrint ( integer i ); 4 automatic int x ; 5 integer y = i ; 6 x = i ; 7 #( x ); //Here the delay is equal to input value 8 #( i ); //Here the delay is the value of last called delayPrint task. 9 y = i ; 10 $display ( "Time(%0t) : i = %0d x = %0d y = %0d" , $time , i , x , y ); //Here i = most recent calls input, x = value input to this task, y = most recent functions input. 11 endtask 12 13 initial 14 begin 15 fork 16 delayPrint ( 3 ); //Delay would be 3 + 5 17 delayPrint ( 5 ); //Delay would be 5 + 5 18 join 19 end 20 endmodule The output of this program will be some thing like: Time(