amvrao's blog

Syntax The basic python syntax does not rely on the braces as in conventional programming. The python relies on indentation of the code. Each indentation level marks the new scope of the code. Data Types:: Variables: The variables in the python are simply like the c variables they dont need any $/@ prefixes.

1 2 module test ; 3 4 int a [ $ ][]; 5 int b []; 6 int c []; 7 8 int aa [][ $ ]; 9 int bb [ $ ]; 10 int cc [ $ ]; 11 12 initial 13 begin 14 b = new [ 10 ]; 15 b [ 0 ] = 100 ; 16 a .push_back ( b ); 17 c = a .pop_back (); 18 $display ( "Read back value is: %0d \n " , c [ 0 ]); 19 20 aa = new [ 10 ]; //Make 10 wide queues. 21 bb .push_back ( 1000 ); 22 aa [ 0 ] = bb ; 23 cc = aa [ 0 ]; 24 $display ( "Read back value from que is: %0d \n " , cc .pop_back ()); 25 26 end 27 28 endmodule

There is a gotcha in the Verilog where you find very trouble in debugging the tasks in the modules. You got to be careful as all the entities in the module are static rather than dynamic. 1 2 module test ; 3 task delayPrint ( integer i ); 4 automatic int x ; 5 integer y = i ; 6 x = i ; 7 #( x ); //Here the delay is equal to input value 8 #( i ); //Here the delay is the value of last called delayPrint task. 9 y = i ; 10 $display ( "Time(%0t) : i = %0d x = %0d y = %0d" , $time , i , x , y ); //Here i = most recent calls input, x = value input to this task, y = most recent functions input. 11 endtask 12 13 initial 14 begin 15 fork 16 delayPrint ( 3 ); //Delay would be 3 + 5 17 delayPrint ( 5 ); //Delay would be 5 + 5 18 join 19 end 20 endmodule The output of this program will be some thing like: Time(