Skip to main content

VCS dynamic reconfiguration for pre-compiled IPs

VCS® MX/VCS® MXi™ LCA Features Guide > Dynamic Reconfiguration at Runtime > Pre-compiled IP Use Model with Dynamic Reconfiguration at Runtime > Test Case

Test Case

In this test case, the top-level module named top instantiates a module named test with the instance names inst_test and a module another module named dut with the instance name inst_dut. The module dut which instantiates twice a module named pe_main with the instance names inst_pe_main1 and inst_pe_man2. This source file also has a substitute module named pe_sub as shown in the following code:
//basic.v
module pe_main;
bit b;
logic l;
endmodule
 
module dut;
pe_main inst_pe_main1();
pe_main inst_pe_main2();
bit out;
endmodule
 
module top;
dut inst_dut();
test inst_test();
endmodule
 
 
module test;
initial begin
#10 top.inst_dut.inst_pe_main1.b=1'b1;
#10 top.inst_dut.inst_pe_main2.l=1'b1;
#100 $finish();
end
endmodule
 
module pe_sub;
endmodule
 
Figure 23-4 Test Case
In this test case, the compile-time configuration file is named config.txt:
//config.txt
replace module {pe_main} with module {pe_sub};
 
This configuration file specifies the possible replacement of an instance of module pe_main with an instance of module pe_sub.
The compile-time command lines are as follows:
% vlogan –sverilog basic.v –work lib1
% vcs –genip lib1.dut -allxmrs +optconfigfile+config.txt
% vcs –integ lib1.top -allxmrs +optconfigfile+config.txt
 
VCS MX displays the following information message from dynamic reconfiguration:
DYNAMIC RECONFIG> Replacing tpe_main With pe_sub Enabled
 
At runtime, write another configuration file by specifying the hierarchical name and the module instances that you want to replace. In this test case, the configuration file is named runconfig.txtas shown:
//runconfig.txt
top.inst_dut.inst_pe_main2
 
This configuration file specifies that you want the module instance with the hierarchical name to be top.inst_dut.inst_pe_main2 replaced. The other instance of module pe_main, with the hierarchical name top.inst_dut.inst_pe_main1 is not replaced.
The runtime command line for this dynamic reconfiguration is as follows:
% simv -dynaconfig runconfig.txt
 
Before simulation, VCS MX replaces this instance with an instance of the substitute module specified in the compile-time configuration file, an instance of module test_sbst.
Also, before simulation VCS MX displays the following information message:
DYNAMIC RECONFIG: Instance top.inst_dut.inst_pe_main2 is replaced with module (pe_sub)

Comments

Post a Comment

Popular posts from this blog

Virtual Sequence and Virtual Sequencer in UVM

Virtual sequences and sequencers in UVM are just virtual containers of multiple sequences and sequencers. Using virtual sequencers and sequences can be done in these three ways: Using only virtual Sequence and handles of sequencers inside the virtual sequence. Using Virtual sequencer to hold the sequencers Same as step 2, by using uvm_declare_p_sequencer. Virtual Sequencer does not create any sequencer objects, rather it points to other physical sequencers in different agents.  Virtual Sequencer extends from uvm_sequencer. Virtual sequence will create its sequences and start them. Running sequences can be controlled by user in the body() task. virtual sequence extends from uvm_sequence. METHOD-1: In this method, we will have one base virtual sequence which will hold the handles to different sequencers. Here we dont use any virtual sequencer. We just use the nested seqeunces with handles ot sequencers inside sequence itself. //This is the base virtual se...
1 comment
Read more

Verdi Uses - I

COVERAGE While going through some of the blog posts, i found that the Verdi supports even coverage right out of the box, but from the 2014 Version. Well till now, we relied on the URG reports and the DVE to review the coverage and apply waivers and create exclusion files. Looks verdi supports all the features.. I did not get any hands on the features of this option, soon i will find some time to play around with this option of coverage in Verdi. How to launch the verdi with coverage. $> verdi -cov -covdir <PATH_TO_TB>.simv.vdb -covdir <PATH_TO_TEST1>.simv.vdb -covdir <PATH_TO_TEST2>.simv.vdb...  You can pass multiple covdirs, where in all the results will be merged. References: SYNOPSYS SITE Think Verification  
Post a Comment
Read more

Good uses of System Verilog DPI..

What is DPI?? Well, The easiest answer is Direct Programming Interface. The DPI is used to communicate the system verilog/ Verilog code to any other language. Well DPI has its own advantages over PLI.  You can check out the differences between the DPI and PLI   HERE . With DPI, you can directly call the c-functions from system verilog code and vice versa. With lot of SOCs and complicated chips in the silicon industry, sometimes you cannot completely live with the generic UVM/System verilog to write complete stimulus for complete chip.  Basics of DPI, Basics of DPI can be found when you google it.  There are some interesting cases where you will find the uses of DPI. I will get through some advanced take aways from IEEE 1800.2012 LRM. You cannot export the objects with in class. You can export only from static objects. exporting the tasks/functions should be in a module/program/interface scope.[or any static scope] . ..... Bear with me as th...
2 comments
Read more