Skip to main content

TODO

Interrupt sequences
Virtual sequence and sequencer
Virtual classes?
score boards and subscribers
unique variables without using rand: uses suffle method of array.
Phase jump
sequence grab and ungrab
good practice: in reset phase reset all variables.. and states in tb/components.
uvm callbacks.
uvm objections. what is the best place to include them?
uvm config db and resource db
UVM report catcher.
UVM phasing.
How does UVM start execution.

UVM questions:
 multiple drivers to one sequencer
multiple sequencers to one driver.
User defined /custom phases How to use?
Driver with request and response.
Differences between lock and grab
set different arbitration types for sequencer?
sequencer arbitration at item level or arbitrate at sequence level.
assertions and properties. complex uses.
uvm_domain
multi dimensional array constraints.
phase ready to end.
Processes and fork and join examples with scopes.
force: -deposit, -freeze and -drive differences.
Sequence layering


SV:
- queues, mailboxes what happens when full and empty?
- constraints both in class and inline what happens?
- clocking blocks and uses?
Event regions


pre-processing in verilog/systemverilog.
gcc/g++ common flags



Comments

Post a Comment

Popular posts from this blog

Verdi Uses - I

COVERAGE While going through some of the blog posts, i found that the Verdi supports even coverage right out of the box, but from the 2014 Version. Well till now, we relied on the URG reports and the DVE to review the coverage and apply waivers and create exclusion files. Looks verdi supports all the features.. I did not get any hands on the features of this option, soon i will find some time to play around with this option of coverage in Verdi. How to launch the verdi with coverage. $> verdi -cov -covdir <PATH_TO_TB>.simv.vdb -covdir <PATH_TO_TEST1>.simv.vdb -covdir <PATH_TO_TEST2>.simv.vdb...  You can pass multiple covdirs, where in all the results will be merged. References: SYNOPSYS SITE Think Verification  
Post a Comment
Read more

Sequence Layering in UVM

What is Sequence Layering? Sequence layering is refered to as running sequences inside sequences.  So whats the big deal. There are virtual sequences we will use to run multiple sequences. A generic example of sequence layering. you have two sequences  Interrupt sequence register read write sequence. Generally when you have interrupt, we generally enter into interrupt service routine, which can be implemented as an interrupt sequence. So when you run an interrupt sequence, you might end up running register read /write sequence like polling or clearing interrupts. Well thats easy, just run one sequence in another. class top_seq extends uvm_sequence#(txn_item); //Two sequencers say.. sub sequences. sub_seq1 seq1; sub_seq2 seq2; ... task body(); seq1.start(some_seqr); seq2.start(some_seqr2); endtask endclass Killing sequences: That was great you are running nested sequences. But how to kill them when needed. UVM provides method cal
2 comments
Read more

SystemVerilog: Mailboxes and Queues

Mailboxes and queues are couple of basic data constructs of system verilog language. Lets get to the definition of them: Queue: A Queue in system verilog function as the name suggests. But with a twist. Queue in system verilog is a list of similar elements. Queue is built on top of an array. Delcaration of a queue. < TYPE > < que_name >[ $ ]; Default Behaviour: The default size of the queue in system verilog is " Infinite ". The above declaration will create a que of infinite length. You can add elements to the que until your simulator crashes :) What if you want to create a queue of finite length. Just look at the declaration below: < TYPE > < que_name >[ $ :< LIMIT >]; The above declaration will create a queue of size " LIMIT+1 " Initializing queue with elements Accessing elements of a queue Methods in queue Inserting elements into queue Reoving elements from queue http://www.project-veripage.com/queue_1.ph
1 comment
Read more