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Standards


  • Verilog
  • System Verilog
  • UPF
    • IEEE-1801
  • PSS

  • UVM
    • IEEE1800.2 -2017

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Verdi Uses - I

COVERAGE While going through some of the blog posts, i found that the Verdi supports even coverage right out of the box, but from the 2014 Version. Well till now, we relied on the URG reports and the DVE to review the coverage and apply waivers and create exclusion files. Looks verdi supports all the features.. I did not get any hands on the features of this option, soon i will find some time to play around with this option of coverage in Verdi. How to launch the verdi with coverage. $> verdi -cov -covdir <PATH_TO_TB>.simv.vdb -covdir <PATH_TO_TEST1>.simv.vdb -covdir <PATH_TO_TEST2>.simv.vdb...  You can pass multiple covdirs, where in all the results will be merged. References: SYNOPSYS SITE Think Verification  
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Virtual Sequence and Virtual Sequencer in UVM

Virtual sequences and sequencers in UVM are just virtual containers of multiple sequences and sequencers. Using virtual sequencers and sequences can be done in these three ways: Using only virtual Sequence and handles of sequencers inside the virtual sequence. Using Virtual sequencer to hold the sequencers Same as step 2, by using uvm_declare_p_sequencer. Virtual Sequencer does not create any sequencer objects, rather it points to other physical sequencers in different agents.  Virtual Sequencer extends from uvm_sequencer. Virtual sequence will create its sequences and start them. Running sequences can be controlled by user in the body() task. virtual sequence extends from uvm_sequence. METHOD-1: In this method, we will have one base virtual sequence which will hold the handles to different sequencers. Here we dont use any virtual sequencer. We just use the nested seqeunces with handles ot sequencers inside sequence itself. //This is the base virtual se...
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Good uses of System Verilog DPI..

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